• Introduction

There are many classes of frequency synthesizer.  Some are open loop and some designs employ  closed loop feedback in one or more loops.   The particular type chosen is a function of the application and  performance requirements.

Broadly speaking, the majority of frequency synthesis designs can be classified as either:

1) Direct Analog (mix/divide) Synthesis

In this design, a reference is applied to a mixer in order to generate new frequencies.  The mixer can be of the active variety or as simple as a passive diode based mixer.  A divider circuit can be used to scale the frequency downward.

This is an open loop design.  As there is no correction feedback loop in this design, this type of synthesizer yields extremely high spectral purity.  Since there is no loop filter, this design also offers very high switching times.

A big drawback is that multiple crystal references are required in order to cover a large range of synthesized frequencies.

This was the first technique employed to synthesize new frequencies and it is still used in applications that require the highest performance invariant to cost and size.

2) Direct Digital Synthesis

This is another "Direct" approach.  This design constructs the new frequency from "scratch".

A phase accumulator correlates the master clock with a control word within a given time window.  This defines a ramp signal composed of phases between 0 and 360 degrees.  Since the rate of change of phase is equal to frequency, and the time window is know, a frequency is derived.  A phase mapper can create a series of digital amplitudes corresponding to the phases.  Then a D/A can convert the digital words to an analog signal.

Some advantages are very fine tuning resolution and fast switching speeds.

One drawback of this approach is that the highest frequency that can be synthesized is one half the clock rate.

3) PLL Synthesizer

This is the most common and most versatile frequency synthesis technique.

In this design, a free running crystal oscillator generates a reference signal.  This signal drifts over time and temperature.  A feedback loop is added to correct for errors between the commanded frequency and the actual frequency.  The error signal is used to drive the oscillator output frequency to the desired target frequency.

Some advantages of the PLL synthesizer are lower cost, flexibility and good spurious suppression.

A major disadvantage of this class of synthesizer is that phase noise performance is inversely proportional to the tuning resolution.  This is because as the division ratios increase, more noise is introduced which impacts the phase noise.  In addition, the higher the division ratio, the longer it takes to lock on to the desired commanded frequency.  Another disadvantage is that the characteristics of the low pass filter used in the feedback loop gates the switching speed of the PLL synthesizer.

Hybrid designs (Digital PLL (DPL) Synthesizers) can be used to get the best of both worlds in some cases.  For example, high resolution can be maintained without adversely impacting phase noise by utilizing two PLLs in one circuit.   One can be used for coarse tuning while one can be used for fine tuning, thus eliminating the need for small step sizes over a large tuning range.

Similarly, switching speeds can be improved by digitally generating a control word to the oscillator prior to the loop retuning via feedback.   Care must be taken here to ensure that the jump in frequency does not put the loop out of "capture range".

• Classical System Block Diagram of PLL synthesizer

Here we focus on the basic PLL synthesizer.

Any linear, time-invariant system can be characterized by it's transfer function, which is the ratio of the output of the system to the input of the system.

By taking the Laplace Transform of the time domain transfer function, the frequency domain transfer function can be found.

The transfer function can be described by polynomials in the numerator and denominator.

The roots of the characteristic equation in the numerator are called the "zeroes" of the system.

The roots of the characteristic equation in the denominator are called the "poles" of the system.

One way to analyze the behavior of system is to examine the poles and zeroes in the complex "s" plane.

The "Type" of a PLL refers to the number of poles at the origin of the s plane.

The Order" of a PLL refers to the total number of poles.

• Components

These are the basic components of the PLL frequency synthesizer.   Each one of these components will be explored in more detail in a future app note.

Crystal Oscillator (reference)

Phase Detector

VCO

Divide by N

Loop Filter

 

• Transfer function

  Although the PLL is a nonlinear device (due to the non-linear nature of the phase detector), under certain conditions (when it has achieved lock), the PLL can be modeled as a linear control system.
  

  

The "Loop Bandwidth", w_p , is defined as the frequency where the open loop gain ( G(s)H(s) ) is equal to unity.

The "Phase Margin",  Ø_p , is defined as the delta between the phase at unity gain and -180^· .

In order to ensure stability, the frequency at which unity gain is achieved must be reached prior to the phase

reaching 180^· .

• Performance Metrics

Frequency of operation

Tuning Resolution (step size)

Tuning Range

Switching Speed

Phase Noise

Spurious content

Capture Range

Lock Range

The next app note in this series will focus on the system level behavior of PLL frequency synthesizers in more detail.